ITD LabITD Lab

Join the Lab

Open thesis topics and research positions.

Bachelor

Bearing fault detection on edge devices

Build a low-power pipeline (preprocessing + classical ML) that runs on an MCU and detects early-stage bearing faults from raw accelerometer data.

Requirements

  • Background in Mechatronics / Electrical / Computer Engineering
  • Comfortable with Python, basic signal processing
  • Bonus: C/C++ on microcontrollers
Master

Transfer learning across machines

Reduce the domain gap between simulated vibration data and real measurements using DANN, CORAL or MMD strategies.

Requirements

  • Solid Python + PyTorch / TensorFlow
  • Understanding of CNN/Transformer architectures
  • Interest in domain adaptation literature
Master

Digital twin for rotating machinery

Build FEA + multibody digital twins (ANSYS, MSC Adams) to generate labeled fault data for downstream AI training.

Requirements

  • ANSYS / MSC Adams experience
  • Strong mechanics fundamentals
  • Comfortable bridging simulation and ML pipelines

How to apply

Send a short email with your CV and a paragraph on why this topic interests you.

du.nguyentrong@hust.edu.vn

Contact

Address
Room 633M-C7, Building C7, 1 Dai Co Viet Street, Hai Ba Trung, Hanoi